Recent News
December 18, 2014

Altera Demonstrates Industry’s Highest Performance DDR4 Memory Data Rates in an FPGA

Altera today announced it is demonstrating in silicon DDR4 memory interfaces operating at an industry-leading 2,666 Mbps. Altera’s Arria® 10 FPGAs and SoCs are the industry’s only FPGAs available today that support DDR4 memory at these data rates, delivering a 43 percent improvement in memory performance over previous generation FPGAs and a 10 percent improvement in memory performance over competing 20 nm FPGAs. Hardware designers today can use the latest Quartus® II software v14.1 to enable 2,666 Mbps DDR4 memory data rates in Arria 10 FPGA and SoC designs. A video demonstration showing robust memory interfaces operating at 2,666 Mbps with margin is available for viewing at www.altera.com/arria10(more)

December 15, 2014

Altera Quartus II Software v14.1 Enables TFLOPS Performance in Industry’s First FPGA with Hardened Floating Point DSP Blocks

Altera today released its Quartus® II software v14.1 featuring expanded support for Arria® 10 FPGAs and SoCs, the FPGA industry’s only devices with hardened floating point DSP blocks and the industry’s only 20 nm SoC FPGAs that integrate ARM processors. Altera’s latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. The software also includes several optimizations that improve designer productivity by accelerating Arria 10 FPGA and SoC design time. (more)

December 04, 2014

Altera SDK for OpenCL Recognized as Design Tool of the Year at the 2014 Elektra Awards

Altera today announced Electronics Weekly magazine selected the Altera SDK for OpenCL as  its design tool of the year at the annual Elektra European Electronics Industry Awards gala in London. These accolades represent the latest in a series of awards and recognitions the Altera SDK for OpenCL has received since its release in 2012. Today, Altera offers the industry’s only OpenCL-conformant solution that allows software programmers to easily implement OpenCL applications on FPGA accelerators. (more)

November 25, 2014

Altera FPGAs and IP with New Functional Safety Development Board and Reference Designs Reduce SIL 3 Development and Certification Costs for Industrial Designs

Altera today announced the availability of a functional safety  development board and FPGA reference designs through NewTec, a leading European provider of safety-related electronic systems. The new board and reference designs coupled with Altera’s TÜV Rheinland-qualified FPGAs, tools, and IP, enable customers to accelerate development and certification of FPGA-based system designs. Altera is demonstrating this and other offerings at SPS IPC Drives 2014, from November 25-27 at the Altera stand # 270 in Hall 3. Altera’s functional safety data package includes comprehensive device support, enhanced software design flows and IP for functional safety system design, allowing customers using Cyclone® FPGAs to reduce risks and cost-effectively meet safety-critical system requirements across product lines. (more)

November 20, 2014

Altera to Exhibit Comprehensive Solution Portfolio for Accelerating Intelligent Automation at SPS IPC Drives 2014

Altera today announced that it will demonstrate industrial solutions based on its field-programmable gate arrays (FPGAs) and SoCs at the SPS IPC Drives conference in Nuremberg, Germany, from November 25 to 27. Altera will share how industrial systems designers can use its FPGAs and SoCs to significantly reduce cost and time to market for factory automation system designs. (more)

November 17, 2014

Altera and IBM Unveil FPGA-accelerated POWER Systems with Coherent Shared Memory

Altera and IBM unveiled the industry’s first FPGA-based acceleration platform that coherently connects an FPGA to a POWER8 CPU leveraging IBM’s Coherent Accelerator Processor Interface (CAPI). This reconfigurable hardware accelerator features shared virtual memory between the FPGA and processor which significantly improves system performance, efficiency and flexibility in high-performance computing (HPC) and data center applications.
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November 14, 2014

Altera CEO John Daane Receives 2014 Robert N. Noyce Award from Semiconductor Industry Association

Altera today announced that President, CEO and Chairman of the Board John P. Daane is this year’s recipient of the prestigious Semiconductor Industry Association (SIA) Robert N. Noyce Award. Daane was presented the award by Dr. John E. Kelly, senior vice president and director of IBM research and 2014 SIA chairman, before the semiconductor industry’s top leaders and more than 400 SIA members at the annual SIA dinner held at the Fairmont Hotel in San Jose on November 13, 2014. Selected by the SIA Board of Directors and members, the award recognizes Daane’s sustained contributions to advancing the semiconductor industry both in the United States and throughout the world. (more)

November 13, 2014

Altera Highlights Its FPGA-Acceleration Technology for Software Programmers at SuperComputing 2014

Altera will demonstrate its FPGA-based acceleration technologies to system designers and software programmers at SuperComputing 2014 (SC14). Altera’s participation at SC14 includes several demonstrations that show how FPGA accelerators are being used to increase performance, lower power consumption and lower latency in high-performance computing, networking and storage applications. FPGA-accelerated systems can deliver a significant performance-per-Watt advantage over standard CPU- and GPU-based servers. Altera is showcasing in its booth various FPGA acceleration technologies and programmer-friendly tools including the industry’s first FPGAs capable of up to 1.5 TFLOPS of throughput and the industry’s only OpenCL-conformant solution for FPGAs. SC14 is being held in New Orleans, Louisiana from November 17-20. (more)

November 05, 2014

Altera and MathWorks Deliver Unified Model-Based Design Workflow for Altera SoCs

Altera today announced new programming support for its ARM-based SoCs using industry-standard workflows from MathWorks. Release 2014b from MathWorks includes an automated, highly integrated model-based design workflow optimized for Altera SoCs. Designers using this flow can accelerate their algorithmic designs in Altera SoCs while staying in a high-level programming environment and save weeks of development time. (more)

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