Altera Announces Industry’s First IEEE 754-compliant Hardened Floating-point DSP Blocks in Currently Shipping Arria 10 FPGAs
San Jose, Calif., April 22, 2014– Altera Corporation (Nasdaq: ALTR) today changed the game as it relates to floating-point DSP performance in an FPGA. Altera is the first programmable logic company to integrate hardened IEEE 754-compliant, floating-point operators in an FPGA, delivering unparalleled levels of DSP performance, designer productivity and logic efficiency. The hardened floating point DSP blocks are integrated in Altera’s 20 nm Arria 10 FPGAs and SoCs – currently shipping – as well as 14 nm Stratix 10 FPGAs and SoCs. Integrated hardened floating-point DSP blocks, combined with an advanced high-level tool flow, enable customers to use Altera’s FPGAs and SoCs to address an expanding range of computationally intensive applications, such as high-performance computing (HPC), radar, scientific and medical imaging.
The hardened single-precision floating point DSP blocks included in Arria 10 and Stratix 10 devices are based on Altera’s innovative variable precision DSP architecture. Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, Altera’s resource efficient, hardened floating point DSP blocks eliminate nearly all the logic usage required for existing FPGA floating-point computations. This game-changing technology enables Altera to deliver up to 1.5 TeraFLOPs (floating point operations per second) DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices. DSP designers are able to choose either fixed or floating-point modesand the floating point blocks are backwards compatible with existing designs.
“The implementation of IEEE 754-compliant floating-point DSP blocks in our devices is truly a game-changer for FPGAs,” said Alex Grbic, director of software, IP and DSP marketing at Altera. “With hardened floating point, Altera FPGAs and SoCs offer a performance and power efficiency advantage over microprocessors and GPUs in an expanded range of applications.”
FPGAs Deliver the Highest Performance-per-Watt
FPGAs feature a fine-grained, highly pipelined architecture that make them ideally suited for use as high-performance compute accelerators. The inclusion of hardened floating-point DSP blocks enable customers to use Altera FPGAs to address the world’s most complex HPC problems in big data analytics, seismic modeling for oil and gas industries and financial simulations. Across these and many other computationally intensive applications, FPGAs deliver the highest performance per Watt when compared to DSPs, CPUs and GPUs.
Save Months of Development Time
The integration of hardened floating-point DSP blocks in Altera FPGAs and SoCs can reduce development time by upwards of 12 months. Designers can translate their DSP designs directly into floating-point hardware, rather than converting their designs to fixed point. As a result, timing closure and verification times are dramatically slashed. Altera also provides multiple tool flows that allow hardware designers, model-based designers and software programmers to easily target the high-performance floating-point DSP blocks in its devices.
- DSP Builder Advanced Blockset offers a model-based design flow that allows designers to go from system definition and simulation to system implementation in a matter of minutes using the industry-standard MathWorks Simulink tools.
- For software programmers, Altera pioneered the use of OpenCL for programming FPGAs and today offers a publicly available C-based, high-level design flow that targets FPGAs. The Arria 10 FPGA floating-point DSP blocks combined with an easy-to-use development flow provide software programmers direct translation to hardware which helps reduce development and verification time.
Based on TSMC 20SoC process technology, Arria 10 FPGAs and SoCs provide the industry’s highest capacity and highest DSP resources in a monolithic die. The use of patented redundancy technology enables Altera to build the industry’s highest density 20 nm FPGA die containing 1.15 million logic elements (LEs). Arria 10 devices deliver 15 percent higher performance than the fastest 28 nm high-end FPGAs and up to 40 percent lower power than the previous 28 nm Arria family.
20 nm Arria 10 devices are the industry’s only FPGAs to feature hardened floating-point DSP blocks, as well as the only 20 nm SoCs that embed a hardened ARM® Cortex®-A9 processor system into the FPGA fabric. The devices offer 4X more bandwidth versus the previous generation and deliver many other features optimized for high-performance applications. Arria 10 device features include:
- Serial transceivers operating up to 28.3 Gbps for chip-to-chip/chip-to-module interfaces
- Backplane support up to 17.4 Gbps
- Up to 96 transceiver channels in a single device
- Dual-core ARM Cortex-A9 processor system
- Hardened floating point DSP blocks
- Support for next-generation memories, including DDR4 at an industry-leading 2666 Mbps and high-speed serial memory support with Hybrid Memory Cube interoperability
Altera 20 nm Arria 10 FPGAs with hardened floating-point DSP blocks are available now. Floating-point design flows, including demonstrations and benchmarks, that target the hardened floating-point DSP blocks in Arria 10 devices will be available in the second half of 2014. Customers can start designing today with Arria 10 FPGAs using soft implementations of floating point and then seamlessly migrate to hardened floating point implementation when the design flows are available.